1. Field of the Invention
The present invention relates to an asynchronous data holding circuit, and particularly, to an asynchronous data holding circuit which holds a data signal synchronized with a clock of the source, in synchronization with a clock of the destination.
2. Description of the Related Art
Conventionally, clock signals are used for transferring data between registers. For example, a circuit which transfers data from a register to another register by using the same clock signal is well known (for example, refer to Japanese Patent Application Laid-Open (JP-A) No. 11-103238).
Even in a circuit in which a frequency of a clock signal is different between a transfer source register and a transfer destination register, data is transferred. In this case, an asynchronous data handoff circuit configured as shown in FIG. 8 is generally used.
A source data register 322 acquires source data of n bits at a rising edge of a source end clock and outputs the n-bit data in synchronization with the source end (i.e., communication) clock. A D flip flop 328A receives a destination (i.e., receiving) end enable signal at the rising edge of the source end clock, the signal is synchronized with the source end clock using two stages synchronization of the D flip flop 328A and a D flip flop 328B, and the synchronized enable signal is output to a source data holding register 324 as a write enable signal. The n-bit data supplied from the source data register 322 is stored in the source data holding register 324 when the enable signal output from the D flip flop 328B is 1. The use of the terminologies “source end clock” and “receiving end clock” in describing the aforementioned conventional circuit herein can be seen as being respectively analogous to “communication clock” and “system clock” used in describing the present invention. Moreover, the terminology “destination” is interchangeably used with “receiving”, such as in “destination end” and “receiving end.” Hence, “destination end” or “receiving end” should be understood as specifying “system end” or a system-side of a circuit.
At the rising edge of the destination end enable signal and the destination end clock, a D flip flop 330 acquires the destination end enable signal and outputs the write enable signal to a destination end data storage register 326, and the output of the source data storage register 324 is stored in the destination end data storage register 326.
In the above circuit structure, when the frequency of the source end clock is higher than that of the destination end clock, as shown in FIG. 9, the destination end enable signal turned active (=1) at timing T1 is output to the source data storage register 324 at timing T3 in synchronization with the source end clock, and the n bit source data is stored in the source data storage register 324 at timing T5, T7, and T8. The output of the source data storage register 324 is acquired into the destination end data storage register 326 at timing T11 in response to the enable signal output from the D flip flop 330 and the destination end clock. In this way, data can be transferred without missing.
On the other hand, when the frequency of the source end clock is lower than that of the destination end clock, as shown in FIG. 10, the destination end enable signal turned active (=1) at timing T1 falls down at timing T2. Therefore, the destination end enable signal is not active when the source end clock rises up at timing T3, and as a result of this the data will not stored in the source data storage register 324.
As described above, in the conventional asynchronous data handoff circuit, when the frequency of the source end clock is lower than that of the destination end clock, data may not be transferred in some phase difference and there is the possibility of missing some pieces of data.